CompCertTSO: A Verified Compiler for Relaxed-Memory Concurrency
Journal of the ACM, 2013 · paper · Computer science
Describes ClightTSO, a concurrent C-like language exposing x86's TSO memory model, and CompCertTSO, a Coq-verified compiler to x86 assembly. Any permitted behavior of the compiled code is also possible in the source semantics; verified fence-elimination optimizations are included.
Checked: PDF from people.mpi-sws.org, fetched 4 Oct 2026. Page numbers are those of that PDF.
2 findings
Wording §6.3.1 (p.40): 'the analysis will have returned ⊥ and so, according to ∼, the thread's buffer is empty'. The relation was introduced as 's R t'; the symbol ∼ is never defined.
- p. 40 §6.3.1 Fence Elimination 1
according to ∼, the thread’s buffer is empty
Judge's note: The image shows a tilde. A grep of the full text finds ∼ only at this place. The relation defined just above is R, and condition (iii) is the one meant.
Second check: another model agreed
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Wording §7.1: 'while PRE does not further reduce the static number of fences', but in Fig. 14 Fraser's skiplist has 12 under aw+FE2 and 11 under aw+PRE+FE2.
- p. 42 §7.1 last paragraph
while PRE does not further reduce the static number of fences
- p. 42 Fig. 14, Fraser's skiplist row
12
- p. 42 Fig. 14, Fraser's skiplist row, aw+FE2 vs aw+PRE+FE2
Fraser’s skiplist 32 18 19 12 11
- p. 42 Section 7.1, text after Fig. 14
PRE does not further reduce the static number of fences
Judge's note: In the page 42 image of Fig. 14, the skiplist row reads 32 18 19 12 11. Every other row has equal aw+FE2 and aw+PRE+FE2 values. The unqualified statement overstates the result for one row.
Second check: another model agreed
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13 minor (typos and the like; most checked by the judge only)
Wording §1.2 says "for four phases the memory accesses are identical except that some values that are undefined in the source take particular values in the target", but Fig. 3 attaches "(undefined values can become defined)" to only three phases. The fourth phase is never named.
- p. 3 §1.2
Moreover, for four phases the memory accesses are identical except that some values that are undefined in the source take particular values in the target
- p. 18 Fig. 3
(undefined values can become defined)
Only the authors can say what is right here.
Judge's note: I counted the 17 phases in Fig. 3 (p.18). Only three carry the undefined-values annotation: Cstacked→Cminor, LTLin→Linear and MachConcr→Asm. §5.5 (p.34) names only the Cstacked-Cminor and spilling/reloading phases. Taking the intro's 2 whole-system phases, 3 fence phases and 1 register-allocation phase, Fig. 3 leaves 8 exact 1:1 phases and 3 concretizing phases, where the intro gives 7 and 4. Some unannotated phase may also concretize undefined values, but I found no statement saying so. Only the authors can say which phase is the fourth.
Second check: another model agreed
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Wording The proof outline after Theorem 5.1 lists the threadwise phases as ClightTSO→Csharpminor, "each of the non-fence-elimination phases from Cminor to MachAbstr" and MachConcr→Asm. This range leaves out Cstacked→Cminor, which Fig. 3 shows as a threadwise downward simulation, and no whole-system proof listed in the outline covers it.
- p. 19 Proof outline after Theorem 5.1
between each of the non-fence-elimination phases from Cminor to MachAbstr
- p. 18 Fig. 3
Simplification (undefined values can become defined)
- p. 34 §5.5
the Cstacked-Cminor and spilling/reloading phases may change some of the undefined values
- p. 3 §1.2, second contribution
(7 of 17) the memory accesses of source and target are in exact 1:1 correspondence. Moreover, for four phases the memory accesses are identical except that some values that are undefined in the source take particular values in the target
Only the authors can say what is right here.
Judge's note: In Fig. 3 (p.18), Cstacked→Cminor is a single downward arrow inside the §5.5 lifted span. §5.5 (p.34) says this phase uses the concretizing variants of Theorems 4.5/4.7. The outline on p.19 covers Cstacked→Csharpminor and MachAbstr→MachConcr as whole-system proofs, and its threadwise range starts at Cminor, so Cstacked→Cminor appears nowhere. The range presumably should start at Cstacked. Reviewer note 2 in this cluster (four vs three concretizing phases) duplicates C001.
Second check: another model agreed
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Wording §1.2 says "abstracting from the 18 000 or so lines of underlying proof script of these two phases", but Fig. 15 gives 8163 + 6525 = 14 688 proof lines for §5.3 and §5.4, or 20 833 lines counting specs as well.
- p. 4 §1.2 Contributions
abstracting from the 18 000 or so lines of underlying proof script of these two phases
- p. 43 Fig. 15
Csharpminor to Cstacked (§5.3)
- p. 43 Fig. 15, rows Csharpminor to Cstacked and MachAbstr to MachConcr
3421 8163
- p. 4 Section 1 (contributions), third paragraph
abstracting from the 18 000 or so lines of underlying proof
Only the authors can say what is right here.
Judge's note: Fig. 15 (p.43) lists Csharpminor to Cstacked (§5.3) as Specs 3421, Proof 8163 and MachAbstr to MachConcr (§5.4) as Specs 2724, Proof 6525. Neither the proof-only total nor the specs-plus-proof total is about 18 000, and I found no other count of these phases in the text. The figure may come from an earlier version of the development or a different count. Because it is hedged ('or so'), I treat this as a query to the authors.
Second check: another model agreed
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Wording §9: 'There are also more optimization passes, including function inlining, constant propagation, and redundant reload elimination' in CompCert 1.12.1, said to be addable to CompCertTSO, yet Fig. 3 and §5.5 already list constant propagation as a CompCertTSO phase.
- p. 44 §9, paragraph on CompCert 1.12.1
There are also more optimization passes, including function inlining, constant propagation, and redundant reload elimination.
- p. 18 Fig. 3
Constant propagation
Only the authors can say what is right here.
Judge's note: Fig. 3 (p.18) shows a 'Constant propagation' RTL pass, and the text at §5.5 says constant propagation is performed. §9 presents it as a newer pass without saying how the 1.12.1 version differs; the const-locations remark suggests an extended version is meant. The wording is ambiguous.
Second check: another model agreed
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Wording p.33: 'with the exception of the stack pointer, which points to the stack frame in MachAbstr, but in MachConcr points to the frame.' Both halves say the same thing, so the stated exception has no content.
- p. 33 §5.4.2 first paragraph
which points to the stack frame in MachAbstr, but in MachConcr points to the frame
Only the authors can say what is right here.
Judge's note: The page 33 image confirms the wording. As printed, the sentence names no difference between the two pointers, presumably a frame block versus the frame's location in MachConcr stack memory. Only the authors can supply the intended contrast.
Second check: another model agreed
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Wording Footnote 4 (p.34): 'the instruction ADD %eax,%ebx corresponds to the assignment %eax <- %eax + %ebx'. This uses %-prefixed (AT&T) register names with Intel operand order.
- p. 34 Footnote 4
the instruction ADD %eax,%ebx corresponds to the assignment %eax <- %eax + %ebx
Only the authors can say what is right here.
Judge's note: Rests on outside knowledge: in AT&T syntax, which uses %-prefixed registers, the destination is the last operand, so ADD %eax,%ebx means %ebx <- %ebx + %eax. The footnote image matches the quote. The notation and the stated operand order do not agree; the authors should say which syntax they intend.
Second check: another model agreed
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Typo The paper uses "CompCert"/"CompCertTSO" in most places but "Compcert"/"CompcertTSO" in some, e.g. "In CompcertTSO, we represent pointers again as block-offset pairs" (p.12) and "the optimizations present in Compcert 1.5" (p.4).
- p. 12 §4.2 last paragraph
In CompcertTSO, we represent pointers again as block-offset pairs
- p. 4 §1.2
including the optimizations present in Compcert 1.5
- p. 4 §1.2, third contribution
including the optimizations present in Compcert 1.5 that are safe under TSO
- p. 33 §5.5
We have enabled all the CompCert 1.5 optimizations that are sound under the TSO semantics except tail call optimization.
Judge's note: I confirmed the mixed capitalisation on the page images of p.4 and p.12; the text layer has further cases on lines 665-688 and 862. This is cosmetic. Reviewer note 2's tail-call point is not a defect: §5.5 (p.34) says plainly that tail call optimization is sound but not enabled, and the intro's 'safe under TSO' wording is only loose.
Second check: none (judge only)
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Typo §6.3.1: 'Take > to be the empty relation (which is trivially well-founded)', whereas Definition 4.6 names the well-founded order '<'.
- p. 40 §6.3.1
Take > to be the empty relation (which is trivially well-founded)
- p. 15 Definition 4.6
equipped with a well-founded order < on States(T)
Judge's note: Both images confirm the symbols. Because the relation is empty the meaning is unaffected, so this is a cosmetic notation inconsistency.
Second check: none (judge only)
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Typo The Fig. 10 panel labels read "MachAbs Thread State", "MachAbs Memory", "MachConc Thread State" and "MachConc Memory", while the caption and text use MachAbstr/MachConcr.
- p. 31 Fig. 10 panel labels
MachAbs Thread State
- p. 31 Fig. 10 caption
MachConcr and MachAbstr thread states
Judge's note: I confirmed the labels on the p.31 page image. They are abbreviated names, inconsistent with the rest of the paper. This is cosmetic.
Second check: none (judge only)
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Typo p.35: 'our semantic values do not include single-point floating point values' should read 'single-precision'.
- p. 35 §5.6 pseudo-instructions list
do not include single-point floating point values
Judge's note: The image confirms 'single-point'. The context is truncating moves that drop precision, so 'single-precision' is the evident term.
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Typo §6.3.3 (p.42): 'whatever analysis was used to used to decide to perform the insertion' contains a duplicated 'used to'.
- p. 42 §6.3.3
whatever analysis was used to used to decide to perform the
- p. 42 Section 6.3.3, first paragraph
irrespective of whatever analysis was used to used to decide to perform the insertion
Judge's note: Confirmed in the page 42 image.
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Typo §9 (p.45): 'since Sasha and Snir's seminal paper' misspells Shasha, as given in the same sentence's citation '[Shasha and Snir 1988]'.
- p. 45 §9 Related work
since Sasha and Snir’s seminal paper
- p. 45 §9, second paragraph
since Sasha and Snir’s seminal pa-
- p. 45 Sec. 9, memory barriers paragraph
Sasha and Snir’s seminal paper
- p. 45 Section 9 Related Work, memory barrier paragraph
Sasha and Snir’s seminal pa-per on delay set analysis [Shasha and Snir 1988]
Judge's note: The page 45 image confirms 'Sasha' in the prose and 'Shasha' in the citation that follows.
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Typo The first reference entry prints the author's first name as "Martn Abadi and Leslie Lamport. 1991." A letter (the accented í of 'Martín') appears to be missing.
- p. 46 References, Abadi and Lamport 1991
Martn Abadi and Leslie Lamport
- p. 46 References, first entry
Martn Abadi and Leslie Lamport. 1991.
Only the authors can say what is right here.
Judge's note: Rests on outside knowledge: the author's first name is spelled 'Martín'. I looked at the crop of the typeset reference list on PDF page 46. It shows 'Martn Abadi' with no i between 't' and 'n', so this is not an extraction artefact; the text layer (line 2767) matches. The name appears nowhere else in the paper; the in-text citation is surname-only, '[Abadi and Lamport 1991]'. This is cosmetic, most likely an accented character that was lost in BibTeX processing.
Second check: none (judge only)