In-Datacenter Performance Analysis of a Tensor Processing Unit
2017 · paper · Computer science
Evaluates the Tensor Processing Unit, a custom chip used in Google datacenters since 2015 for neural network inference. Against contemporary Intel CPUs and Nvidia GPUs, it is on average about 15–30× faster and 30–80× higher in performance per watt.
Checked: PDF from arxiv.org, fetched 4 Oct 2026. Page numbers are those of that PDF.
5 findings
Substance Table 3 row 4 "Weight stall cycles 53.9% 44.2% 58.1% 62.1% 0.0% 28.1% 43%": the six values average 41.1%, not 43%.
- p. 7 Table 3, row 4 (Weight stall cycles), Mean column
43%
- p. 7 Table 3, row 4 Mean
Weight stall cycles 53.9% 44.2% 58.1% 62.1% 0.0% 28.1% 43%
Judge's note: Page 7 image. Every other Mean entry equals the simple average of its row after rounding (rows 1,2,3,5,6,7,8,9 checked). With 43%, the means of rows 1+4+5+6 sum to 103 although the caption says those rows total 100%. With 41% they sum to 101.
Second check: another model agreed
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Reference or label Table 1 caption cites "DeepMind AlphaGo [Sil16][Jou15]", but the reference list has no [Jou15] entry; the only Jouppi entry is "[Jou16] Jouppi, N. May 18, 2016."
- p. 2 Table 1 caption
DeepMind AlphaGo [Sil16][Jou15]
- p. 16 Reference list
[Jou16]
- p. 16 References
[Jou16] Jouppi, N. May 18, 2016.
Judge's note: The page 2 image shows [Jou15] in the Table 1 caption. A search of the full text finds [Jou15] only in that caption and [Jou16] only in the reference list (p.16 image). The key points to no entry; [Jou16] was probably intended.
Second check: another model agreed
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Reference or label The DianNao-family sentence ends "appear in NN applications [Keu16] [Che16a]", but [Che16a] is Eyeriss (Chen, Emer, Sze). The DianNao Family paper is [Che16b], which the text never cites.
- p. 13 Sec. 9 Related Work, last paragraph
appear in NN applications [Keu16]
- p. 14 Sec. 9, first line
[Che16a]. All use 16-bit integer operations
- p. 16 Reference list
[Che16b] Chen, Y., Chen, T.,Xu, Z., Sun, N., and Teman, O., 2016. DianNao Family
- p. 16 [Che16b]
Sun, N., and Teman, O.
Judge's note: Pp.13-14 crops: the sentence about the DianNao family cites [Keu16][Che16a]. In the reference list on p.16, [Che16a] is the Eyeriss paper and [Che16b] is 'DianNao Family: Energy-Efficient Hardware Accelerators...'. A text search finds [Che16b] only in the reference list. [Che16a] is used correctly for Eyeriss later on p.14. The 'Teman' spelling point in note 4 is handled in C026.
Second check: another model agreed
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Reference or label Sec. 9 cites "[Ros15a][Ros15b][Ros15c][Ros15f][Tho15][You15]", but the reference list has only Ros15a–Ros15d; no [Ros15f] exists.
- p. 14 Sec. 9, Eyeriss paragraph
[Ros15a][Ros15b][Ros15c][Ros15f][Tho15][You15]
- p. 17 Reference list
[Ros15d] Ross, J., Thorson, G., 2015. Rotating Data
- p. 17 Reference list
[Ros15d]
- p. 14 Section 9
[Ros15c][Ros15f][Tho15]
Judge's note: The p.14 crop shows 'Ros15f'. The p.17 reference list runs Ros15a, b, c, d and then Rus15. Sec. 2 (p.3) cites the same group as Ros15a–Ros15d, so the intended key is most likely Ros15d.
Second check: another model agreed
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Reference or label [Liu15] reads "2015, March. Pudiannao: A polyvalent machine learning accelerator. Proceedings of the 42nd International Symposium on Computer Architecture.", but [Du15] dates the same 42nd ISCA "2015, June", so the reference list gives one conference two different months.
- p. 17 Reference [Liu15]
2015, March. Pudiannao: A polyvalent machine learning accelerator. Proceedings of the 42nd International Symposium on Computer Architecture
- p. 16 Reference [Du15]
2015, June. ShiDianNao
- p. 17 Reference [Liu15]
2015, March. Pudiannao: A polyvalent machine learning accelerator. Proceedings of the 42nd International Symposium on Computer Architecture.
Only the authors can say what is right here.
Judge's note: Rests on outside knowledge: that PuDianNao appeared at ASPLOS 2015 (March), not at ISCA. On the page 17 image, [Liu15] reads '2015, March. Pudiannao ... Proceedings of the 42nd International Symposium on Computer Architecture.' On the page 16 crop, [Du15] reads '2015, June. ShiDianNao ... Proceedings of the 42nd International Symposium on Computer Architecture.' The mismatch inside the reference list is plain on the page: the same venue is given two different months. The files alone cannot show whether the month or the venue of [Liu15] is the wrong part, so the authors should check the entry.
Second check: another model agreed
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21 minor (typos and the like; most checked by the judge only)
Wording Introduction bullet says the revised TPU "would be about 30X - 50X faster than the GPU and CPU", but the speedups in Table 6 and Section 7 give a CPU range that goes well beyond 50X under the weighted mean.
- p. 2 Introduction, highlights bullet 5
it would be about 30X - 50X faster than the GPU and CPU
- p. 1 Abstract
would triple achieved TOPS
- p. 12 Section 7
drops TPU’ means from 2.6 to 1.9 and 3.9 to 3.2
- p. 8 Table 6
14.5 29.2
Only the authors can say what is right here.
Judge's note: Table 6 (p.8) gives the TPU vs CPU as 14.5 (GM) and 29.2 (WM), and the TPU vs GPU as 13.2 and 15.3. Section 7 (p.12 text) gives TPU' including host time as 1.9 (GM) and 3.2 (WM). Applied to the GPU, these give about 25X–49X, which roughly matches the stated range. Applied to the CPU, they give about 28X–93X. The abstract's 'triple' points the same way. The bullet seems to mix bases, and only the authors can say how the 30X–50X range was formed.
Second check: another model agreed
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Wording "pack 25 times as many MACs (65,536 8-bit vs. 2,496 32-bit)" (also on p.2): the exact counts printed alongside give a ratio of about 26.3.
- p. 15 Sec. 10 Conclusion
pack 25 times as many MACs (65,536 8-bit vs. 2,496 32-bit)
- p. 2 Sec. 1 highlights
the TPU has 25 times as many MACs
Judge's note: The p.15 and p.2 crops confirm both statements. The MAC counts are exact, and their ratio is 26.26, so '25 times' understates it slightly. It is probably a loose round figure.
Second check: another model agreed
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Wording Table 4 lists the CPU operating point (batch 16, 42% of max IPS) at "7.2 ms", while the caption states "The longest allowable latency is 7 ms".
- p. 8 Table 4, CPU batch 16 row
7.2 ms
- p. 8 Table 4 caption
The longest allowable latency is 7 ms
Only the authors can say what is right here.
Judge's note: Page 8 image. The text presents the CPU at 42% as its operating point under the 7 ms limit, but the 7.2 ms in the table is above that limit. The paper states no tolerance. The authors should say whether the limit was applied loosely or whether the value or limit differs.
Second check: another model agreed
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Wording Text says "118W per die total (TPU+Haswell/2) and 40W per die incremental (TPU in Fig. 10)", but at 100% load Fig. 10 shows the TPU line at 43 W, while 118 W is the 100% total.
- p. 10 Sec. 6, third paragraph
40W per die incremental (TPU in Fig. 10)
- p. 11 Figure 10, TPU (purple) line at 100%
43
Judge's note: Page 10 text and Figure 10 on p.11: the TPU line runs 38→43 and reads 40 only at mid loads. The next sentence's 88% matches 38/43. 40 W matches the measured busy power in Table 2, so the quoted value is defensible, but the sentence pairs a 100%-load total with a figure that is not the 100%-load incremental value.
Second check: another model agreed
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Typo Duplicated word in the CNN definition: "Each ensuing layer is a set of of nonlinear functions of weighted sums".
- p. 2 Sec. 1, item 2
is a set of of nonlinear functions
- p. 2 Introduction, CNN list item
a set of of nonlinear functions
- p. 2 Section 1, item 2 (CNN)
is a set of of nonlinear functions of weighted sums
- p. 2
: Each ensuing layer is a set of of nonlinear functions
Judge's note: The page 2 image, item 2 of the list, shows "set of of".
Second check: code check
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Typo Table 1 caption opens a parenthesis "(FC is fully connected, Conv is convolution, ... Pool is pooling, which does nonlinear downsizing on the TPU; and TPU application popularity in July 2016" and never closes it.
- p. 2 Table 1 caption
the types and number of layers in the NN (FC is fully connected
Judge's note: On the page 2 image, the caption has no closing parenthesis after the layer-type glosses. C005 and C006 report the same defect.
Second check: none (judge only)
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Typo Ungrammatical wording: "the operations per byte need to reach peak performance (roofline knee in Section 4) is ~1350" ('needed' was meant).
- p. 3 Sec. 2, accumulator sizing sentence
the operations per byte need to reach peak performance
Judge's note: The page 3 image shows the text as quoted.
Second check: none (judge only)
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Typo Table 2 caption spells "SECDEC and no Boost mode reduce K80 bandwidth from 240 to 160"; the body text on the same page uses SECDED.
- p. 5 Table 2 caption
SECDEC and no Boost mode reduce K80 bandwidth from 240 to 160
- p. 5 Table 2 caption
SECDEC and no Boost mode reduce K80 bandwidth
- p. 5 Section 3
at least SECDED protection
- p. 5 Section 3
SECDED protection of internal SRAM
Judge's note: The page 5 image shows SECDEC in the caption and SECDED in the Section 3 text.
Second check: none (judge only)
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Typo Stray period in Figure 6 caption: "much further left than in Figure. 5".
- p. 7 Figure 6 caption
much further left than in Figure. 5
Judge's note: The page 7 image shows 'Figure. 5'.
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Typo Two punctuation slips: citation key "[Cau 16]" has a stray space, and the Figure 6 caption says "than in Figure. 5." with a stray period.
- p. 14 Section 9
[Cau 16]
- p. 7 Figure 6 caption
than in Figure. 5.
Judge's note: The p.14 crop shows '[Cau 16]', and the reference list on p.16 uses the same spaced key. The p.7 crop shows 'Figure. 5.'
Second check: none (judge only)
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Typo Table 4 caption repeats a phrase: "per die throughput (IPS) for MLP0 as batch size varies for MLP0".
- p. 8 Table 4 caption
for MLP0 as batch size varies for MLP0
Judge's note: The page 8 image shows the duplication.
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Typo Wrong preposition: "as we scale these parameters over the range for 0.25x to 4x" ('from' was meant).
- p. 10 Sec. 7, second paragraph
over the range for 0.25x to
Judge's note: The page 10 image, Section 7 second paragraph, shows the text as quoted.
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Typo Figure 11 caption has the words in the wrong order: "The weighted mean makes it hard see to contributions of individual DNNs" should read "hard to see contributions".
- p. 11 Figure 11 caption
makes it hard see to contributions of individual
- p. 11 Figure 11 caption
makes it hard see to contributions
Judge's note: The crop of the caption on p.11 shows the wording exactly as quoted.
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Typo Sec. 9 writes the unit as "The 40-Mhz T0" instead of "MHz".
- p. 13 Sec. 9, SPERT-II paragraph
The 40-Mhz T0
Judge's note: The p.13 crop shows '40-Mhz'. Elsewhere the paper writes MHz (e.g. '200 MHz', '700 MHz' on p.14).
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Typo Reference [Far11] gives the venue as "In CVRP 2011 Workshops", presumably meaning CVPR.
- p. 16 Reference [Far11]
In CVRP 2011 Workshops
- p. 16 Reference [Far11]
In CVRP 2011 Workshops.
- p. 16 [Far11]
CVRP 2011 Workshops
Only the authors can say what is right here.
Judge's note: Rests on outside knowledge: the Computer Vision and Pattern Recognition conference is abbreviated CVPR. The p.16 crop shows 'CVRP 2011 Workshops'.
Second check: none (judge only)
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Typo Co-author spelled "Teman, O." in [Che16b] and [Liu15] but "Temam, O." in [Che14a], [Che14b] and [Du15].
- p. 16 Reference [Che16b]
Sun, N., and Teman, O., 2016
- p. 17 Reference [Liu15]
Teman, O., Feng, X.
- p. 16 Reference [Che14a]
Chen, Y. and Temam, O., 2014
- p. 17 Reference [Liu15]
Zhou, S., Teman, O., Feng, X.
Judge's note: The p.16 and p.17 crops show both spellings within the same author group, so the reference list is inconsistent with itself.
Second check: none (judge only)
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Typo The [Asa98] author list is garbled: "Asanović, K. 1998. Asanović, K., Beck, Johnson, J.," repeats the first author and gives 'Beck' without initials.
- p. 16 Reference [Asa98]
Asanović, K. 1998. Asanović, K., Beck, Johnson, J.,
Judge's note: The p.16 crop shows the text exactly as quoted.
Second check: none (judge only)
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Typo The [Cau 16] author list has initials run together: "Haselman, H.A.J.F.M., Humphrey, S.H.M., Daniel, P.K.J.Y.K., Ovtcharov, L.T.M.K., Lanka, M.P.L.W.S. and Burger, D.C.D."
- p. 16 Reference [Cau 16]
Haselman, H.A.J.F.M., Humphrey, S.H.M., Daniel, P.K.J.Y.K.
- p. 16 Reference [Cau 16]
Haselman, H.A.J.F.M., Humphrey, S.H.M., Daniel, P.K.J.Y.K., Ovtcharov, L.T.M.K.
Judge's note: The p.16 crop confirms the text. Other entries give 'Haselman, M.' and 'Burger, D.' ([Put14]), which shows the initials here were merged from neighbouring names.
Second check: none (judge only)
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Typo The reference list puts [Alb16] before [Ado16], breaking the alphabetical order of keys used elsewhere in the list.
- p. 16 Reference list, first entries
[Alb16]
Judge's note: The p.16 crop shows the order Aba16, Alb16, Ado16, Asa02. Alphabetically 'Ado' comes before 'Alb'.
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Typo Stray punctuation in the references: [Ros15b] has "Neural Network Processor, , Patent Application No. 62/164,902." (a doubled comma) and [Keu16] ends "Communications of the ACM, 59(11),." (a stray comma before the period).
- p. 17 Reference [Ros15b]
Neural Network Processor, , Patent Application
- p. 17 [Ros15b]
Neural Network Processor, , Patent
- p. 16 [Keu16]
59(11),.
Judge's note: Both are visible in the page images: the doubled comma in [Ros15b] on page 17 (crop C032-a and the full page) and '59(11),.' in [Keu16] on page 16 (crop C032-c). These are cosmetic punctuation errors, and the fix is obvious: delete the extra comma. A nearby entry, [Ros15d], also lacks a space after its comma ('Computations,Patent'), which is cosmetic as well.
Second check: none (judge only)
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Typo Reference [Pat04] title is misspelled: "Latency lags bandwith" should be "bandwidth".
- p. 17 Reference [Pat04]
Latency lags bandwith
Judge's note: The p.17 crop shows 'bandwith'.
Second check: none (judge only)