Dark Silicon and the End of Multicore Scaling
Proceedings of the 38th annual international symposium on Computer architecture, 2011 · paper · Computer science
Models multicore scaling limits by combining device, single-core and multicore scaling over five technology generations. It finds scaling is power limited: 21% of a chip must be off at 22 nm, over 50% at 8 nm, and average speedup through 2024 is only 7.9×.
Checked: PDF from research.cs.wisc.edu, fetched 4 Oct 2026. Page numbers are those of that PDF.
3 findings
Substance The conservative power scaling is inconsistent. Sec 4.3 says "power will decrease by 74%" and the Table 2 footer says "23% power reduction per node", but the Table 2 conservative 8 nm power factor is "0.22", which is a 78% reduction or about 26% per node.
- p. 3 Table 2, Conservative footer row
6% frequency increase and 23% power reduction per node
- p. 3 Table 2, Conservative 2018 8 nm Power
0.22
- p. 5 Section 4.3, end
power will decrease by 74%
- p. 3 Table 2, Conservative 8 nm row
2018 8 1.34 0.84 0.24 0.22
Only the authors can say what is right here.
Judge's note: Viewed Table 2 on p3 and Sec 4.3 on p5. 1 − 0.22 = 0.78. Five steps of 0.77 give 0.77^5 ≈ 0.27, a 73% reduction, so the text and the footer agree with each other but not with the table. The per-step ratios in the table are 0.71, 0.73, 0.75, 0.74 and 0.76. The table's own columns give C·V²·f = 0.24·0.84²·1.34 ≈ 0.227, close to 0.22. The ITRS counterparts are consistent: 0.12 is an 88% reduction, 3.85 is about 3.9×, and 1.31^5 ≈ 3.86. The conservative frequency figures (6%/node, 1.34 total, 34%) are also consistent. Only the authors can say which conservative power figure is the intended one.
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Substance Sec. 7.6 says 'our validation against real and simulated systems (Section 5.2) shows the model always under-predicts performance', but Sec. 5.2 says 'the model only over-predicts performance, making our speedup projections optimistic' and 'CmpMR consistently over-predicts raw performance'.
- p. 11 Section 7.6 Limitations, last paragraph
shows the model always under-predicts performance
- p. 7 Section 5.2 Model Validation
CmpMR consistently over-predicts raw performance
- p. 7 Model Assumptions / Validation
the model only over-predicts performance, making our speedup projections optimistic
- p. 11 Section 7.6
shows the model always under-predicts
Judge's note: Both passages are in the images (p.11 last paragraph of 7.6; p.7 Model Assumptions and Model Validation). The 7.6 sentence cites Sec. 5.2 to argue that the projections are favourable, which needs over-prediction. 'Under-predicts' states the opposite direction from the cited validation.
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Reference or label Sec. 7.3 says 'as shown in Figure 6 for the 8 nm node (2018)', but Figure 6 is 'at 8 nm with ITRS Scaling', and Table 2 dates the ITRS 8 nm node to 2024 (2018 is the conservative 8 nm year).
- p. 9 Section 7.3, first paragraph
Figure 6 for the 8 nm node (2018)
- p. 9 Figure 6 caption
dynamic topology at 8 nm with ITRS Scaling
- p. 3 Table 2, ITRS rows
2024 8†
- p. 9 Figure 6 caption
at 8 nm with ITRS Scaling
Judge's note: Checked p.9 Sec. 7.3 and the Figure 6 caption, and Table 2 on p.3 (ITRS row '2024 8†'; Conservative row '2018 8'). The experiment and figure use ITRS scaling and quote 'typical ITRS-scaling speedups'. Only the final 6.3× is a conservative figure. The year printed for the node shown in Figure 6 therefore does not match the ITRS timeline.
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20 minor (typos and the like; most checked by the judge only)
Wording Results the paper attributes to ITRS scaling are dated on the conservative timeline: "At 22 nm (i.e. in 2012), 21% of the chip will be dark ... using ITRS scaling" and the abstract's "22 nm (just one year from now)", while Table 2 ITRS gives 22 nm = 2015 and 32 nm = 2012. Sec 7.3 also says "8 nm node (2018)" for Figure 6, which the caption says uses ITRS scaling, while Table 2 ITRS gives 8 nm = 2024.
- p. 1 Abstract
Even at 22 nm (just one year from now), 21% of a fixed-size chip must be powered off
- p. 2 Introduction, finding ii
At 22 nm (i.e. in 2012), 21% of the chip will be dark and at 8 nm, over 50% of the chip will not be utilized using ITRS scaling
- p. 3 Table 2, ITRS rows
2015 22†
- p. 2 Introduction, contribution ii
At 22 nm (i.e. in 2012), 21%
Only the authors can say what is right here.
Judge's note: Checked p1 abstract, p2 contribution (ii), p3 Table 2 and p9 Sec 7.3 and the Fig 6 caption. In Table 2 the ITRS rows are 2010/45, 2012/32, 2015/22, 2018/16, 2021/11, 2024/8. The conservative rows are 2008/45, 2010/32, 2012/22 ... 2018/8. So 2012 for 22 nm and 2018 for 8 nm are conservative-timeline years, but they are attached to ITRS results. The conclusions mix the two timelines in the same way: '2024 at 8 nm' and also 'the path to 8nm in 2018'. Nothing in the paper says why. The node values are right and only the year labels conflict, so this goes to the authors as a query. Reviewer note 7's remark about the '24-fold gap' is handled under C002.
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Wording Abstract: "only 7.9× average speedup ... leaving a nearly 24-fold gap from a target of doubled performance per generation". The 24 is the difference 32 − 7.9, not a ratio, and the ratio is about 4×. Sec 7.5's "gap is at least 13×" / "22×" uses the same difference-as-fold wording.
- p. 1 Abstract, last sentence
leaving a nearly 24-fold gap from a target of doubled performance per generation
- p. 1 Abstract
leaving a nearly 24-fold gap
- p. 11 7.5
the gap is at least 13× at 8 nm
Only the authors can say what is right here.
Judge's note: Checked the p1 abstract, p11 Sec 7.5 and Figure 9. Five doublings give a 32× target. 32 − 7.9 = 24.1 matches 'nearly 24'. As a fold change the gap is 32/7.9 ≈ 4.05. In Sec 7.5 the 22× (conservative) and 13× (ITRS) figures also match differences between the Moore's Law curve (32) and the typical upper bound in Fig 9 (about 10 and about 18–19). So the paper consistently computes the gap as a difference but labels it 'fold' or '×'. This is a wording and ambiguity issue only.
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Wording Introduction: "In 2024, will processors have 32 times the performance of processors from 2008, exploiting five generations of core doubling?" This mixes the conservative start year (45 nm = 2008) with the ITRS end year (8 nm = 2024) in Table 2.
- p. 1 Introduction, para 3
In 2024, will processors have 32 times the performance of processors from 2008
- p. 3 Table 2
2010
Judge's note: Checked p1 and Table 2 on p3. On the ITRS timeline 45 nm is 2010 and 8 nm is 2024. On the conservative timeline 45 nm is 2008 and 8 nm is 2018. The 2008 baseline may simply refer to when the real 45 nm processors in the dataset came out, so either reading could be legitimate. It is recorded as a consistency observation linked to C001.
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Wording Table 3's composed core count uses "(TDP−PqL)/P(qS)", which subtracts the large core's power, although Sec 2 says "In either serial or parallel cases, the large core or the small cores are used exclusively". The term is also printed as 'PqL' rather than P(qL).
- p. 5 Table 3, Composed row
TDP−PqL
- p. 2 Section 2, Composed Multicore
In either serial or parallel cases, the large core or the small cores are used exclusively.
Only the authors can say what is right here.
Judge's note: Viewed Table 3 and Sec 5.1 on p5 and Sec 2 on p2. For the dynamic topology, where cores are also used exclusively, the table uses TDP/P(qS), and the text explains that the small-core count is then not limited by the large core's power. The composed large core is made of the fused small cores, but its power is still subtracted, and no text explains why. This may be a deliberate modelling choice, so it is a query rather than a proven error. The missing parentheses are a separate typographic slip.
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Wording Table 1, GPU asymmetric parallel phase, lists "1 Large ST Core + N Small MT Cores (1 Thread) (Multiple Threads)", but Section 2 states "For GPU-like multicores, this study assumes that the single ST core does not participate in parallel work."
- p. 3 Table 1, GPU Multicores, Parallel, Asymmetric
1 Large ST Core + N Small MT Cores
- p. 3 Section 2, paragraph after Table 2
For GPU-like multicores, this study assumes that the single ST core does not participate in parallel work.
Only the authors can say what is right here.
Judge's note: Viewed Table 1 and Sec 2 on p3. The table puts the ST core in the parallel phase for GPU asymmetric, and the text says it does not take part. In Fig 8 (p10) the GPU asymmetric and dynamic panels look nearly identical, which fits the text's assumption, so the table entry is the inconsistent one. The table and the text conflict, and the authors should clarify.
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Wording Sec 4.2: "We used 20 representative Intel and AMD processors at 45 nm (Atom Z520, ..., i7-965 ExEd)" but the parenthetical lists only 19 processors.
- p. 4 Section 4.2, Empirical data for the core model
We used 20 representative Intel and AMD processors at 45 nm
Only the authors can say what is right here.
Judge's note: Counted on the p4 image and in the text: Atom Z520, Atom 230, Atom D510, C2Duo T9500, C2Extreme QX9650, C2Q-Q8400, Opteron 2393SE, Opteron 2381HE, C2Duo E7600, C2Duo E8600, C2Quad Q9650, C2Quad QX9770, C2Duo T9900, Pentium SU2700, Xeon E5405, Xeon E5205, Xeon X3440, Xeon E7450, i7-965 ExEd. That is 19. The list is not marked as partial. Either the count or the list is off by one.
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Wording Eq. (1) bandwidth term 'BWmax / (rm × mL1 × b)' counts every L1 miss as off-chip traffic, while Eq. (3) 't = (1 − mL1)tL1 + mL1(1 − mL2)tL2 + mL1mL2tmem' sends only mL1·mL2 of accesses to memory; the L2 extension is said to be 'completely modeled' by the change to Eq. (3).
- p. 5 Equation (1)
rm × mL1 × b
- p. 6 Equation (3)
mL1mL2tmem
Only the authors can say what is right here.
Judge's note: Checked Eq. (1) on p.5 and Eqs. (3)-(4) and the 'Multi-level caches' paragraph on p.6. The paper says the L2 is handled by 'a small modification to the average memory access time, as shown in Equation (3)', but Eq. (1) still divides BWmax by rm×mL1×b. For CPU designs that have an on-chip L2 (Physical Constraints, p.7), L1 misses that hit in L2 would not use off-chip bandwidth, so the two equations treat memory traffic differently. GPU-like designs have no L2, so the gap does not arise for them. This may be a deliberate simplification carried over from Guz et al., so only the authors can say which is meant.
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Wording Sec. 5.1 says Hill and Marty's [15] 'models describe symmetric, asymmetric, dynamic, and composed multicore topologies', while Sec. 8 says [15] covers 'symmetric, asymmetric, and dynamic multi-core designs'.
- p. 5 Section 5.1
Their models describe symmetric, asymmetric, dynamic, and composed multicore topologies
- p. 11 Section 8 Related Work
including symmetric, asymmetric, and dynamic multi-core designs
Only the authors can say what is right here.
Judge's note: Rests on outside knowledge: that Hill and Marty (2008) modelled symmetric, asymmetric and dynamic multicores but not a composed topology. Both passages are as quoted (p.5 Sec. 5.1; p.11 Sec. 8). Read on their own, 'including' in Sec. 8 is not exhaustive, so the paper does not strictly contradict itself. The two descriptions of [15] still differ, and the composed topology elsewhere in the paper is linked to other work (core fusion [17], composable processors [19]). Only the authors can confirm which description of [15] is meant.
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Wording The speedup baseline is defined as 'the performance of a single Nehalem core at 45 nm as our baseline (PerfB)', with S_R,Serial = PerfS/PerfB and S_R,Parallel = PerfP/PerfB, but elsewhere 'The speedup is computed over a quad-core Nehalem at 45 nm' and results are 'normalized to the performance of a quad-core Nehalem multicore at 45 nm'.
- p. 6 Section 5.2, Multicore Topologies
compute the performance of a single Nehalem core at 45 nm as our baseline (Per fB)
- p. 6 Section 5.2, after Eq. (4)
corresponding to a Quad-core Nehalem at 45 nm
- p. 7 Section 6, third bullet
The speedup is computed over a quad-core Nehalem at 45 nm.
Only the authors can say what is right here.
Judge's note: p.6 Multicore Topologies defines PerfB as a single Nehalem core and uses it in Eq. (5) for both the serial and parallel parts. p.6 (after Eq. 4) speaks of a 'Quad-core Nehalem at 45 nm' baseline, as do the p.7 Sec. 6 bullet, p.8 Sec. 7.2 and p.9 Sec. 7.3. Nothing in the paper explains how a single-core PerfB gives speedups relative to a quad-core chip, for example by normalising afterwards. The authors need to say which baseline was used.
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Wording 'Thus, the model only over-predicts performance' (Sec. 5.2 Model Assumptions) is contradicted in the same paragraph by 'Cache behaviors may lead to over- or under-prediction', by Table 5 entries marked ↓, and by 'CmpMR underpredicts speedups for two benchmarks'.
- p. 7 Section 5.2, Model Assumptions
Thus, the model only over-predicts performance
- p. 7 Section 5.2, Model Assumptions
Cache behaviors may lead to over- or under-prediction.
- p. 7 Section 5.2, Model Validation
CmpMR underpredicts speedups for two benchmarks
Only the authors can say what is right here.
Judge's note: All quotes are on the p.7 image. Table 5 lists 'Thread Data Sharing: 0' as ↓ for CPU and 'Cache Hit Rate Function' as '↑ or ↓'. The Model Validation paragraph reports under-prediction for two benchmarks. So 'only over-predicts' overstates what the paper's own material shows. The wording should be qualified.
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Wording T9900 example: 'core power of 1.88 W' and 'With the 125 W power budget at 8nm, 67 such cores can be integrated', but 67 × 1.88 W exceeds 125 W.
- p. 8 Section 7.1, T9900 example
With the 125 W power budget at 8nm, 67 such cores can be integrated
- p. 8 Section 7.1, T9900 example
core power of 1.88 W
Only the authors can say what is right here.
Judge's note: Checked p.8 Sec. 7.1 and Table 2 on p.3. The printed per-core power matches 15.63 W times the ITRS 8 nm power factor of 0.12 (1.876 W). At that value, 125 W fits 66 cores, not 67. The area limit (111/0.71 ≈ 156) does not bind. With the unrounded factor 3.85×0.62²×0.08 ≈ 0.118, per-core power is about 1.85 W and 67 would fit. The printed numbers are therefore inconsistent with each other only by rounding. Only the authors can say which value was used.
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Wording Sec. 7.5: 'a speedup gap of at least 22× exists at the 8 nm technology node' and 'the gap is at least 13× at 8 nm' appear to be differences from 32, written with the ratio sign '×'.
- p. 11 Section 7.5 Summary
a speedup gap of at least 22× exists at the 8 nm technology node
- p. 11 Section 7.5 Summary
the gap is at least 13× at 8 nm
Only the authors can say what is right here.
Judge's note: In Figure 9 (p.11), the 'Typical CmpMR Upper Bound' at 8 nm reads about 10 (conservative) and about 18-19 (ITRS), against Moore's Law at 32. The quoted gaps match 32−10 and 32−19 rather than the ratios (about 3.2 and 1.7). Elsewhere the paper uses '×' for ratios, so the wording is ambiguous. Values are read from the plot, so they are approximate.
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Typo Typos: "such as FinTETs, will supersede planar bulk" (p3; should be FinFETs) and "per-core power of 15.63 W and are of 22.30 mm²" (p8; should be 'area of').
- p. 3 Section 3 Device Model
such as FinTETs, will supersede planar bulk
- p. 3 Section 3
FinTETs
- p. 3 Section 2
Sandybrige
- p. 8 Sec 7.1
per-core power of 15.63 W and are of 22.30
Judge's note: Both are visible in the page images on p3 (Sec 3) and p8 (Sec 7.1). The 'Sandybrige' misspelling, also mentioned in this cluster, is judged under C009.
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Typo Misspelling: "AMD Fusion and Intel Sandybrige combine CPU and GPU designs" should read "Sandy Bridge".
- p. 3 Section 2, paragraph on heterogeneous configurations
Intel Sandybrige
Judge's note: Visible in the crop of p3, Sec 2.
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Typo Copy-editing errors: 'Multithreaded performance (Perf) of an Multithreaded performance (Perf) of an either CPU-like or GPU-like multicore' (p.5, phrase printed twice); 'FinTETs' for FinFETs (p.3, Sec. 3); 'Sandybrige' for Sandy Bridge (p.3, Sec. 2).
- p. 5 Section 5.2, Microarchitectural Features
Multithreaded performance (Per f) of an Multithreaded performance
- p. 3 Sec 3
FinTETs
- p. 3 Sec 2
Sandybrige
- p. 3 Section 3, Device Model
such as FinTETs, will supersede planar bulk at 22 nm
Judge's note: All three are in the page images: the repeated phrase at the start of 'Microarchitectural Features' on p.5, 'such as FinTETs, will supersede planar bulk at 22 nm' in the right column of p.3, and 'AMD Fusion and Intel Sandybrige' in the left column of p.3. They are print errors, not extraction artefacts.
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Typo Missing space 'We begin the study of future multicoredesigns' (Sec. 7, p.8); subscript 'NComposd' for 'NComposed' in Table 3 (p.5).
- p. 8 Section 7, first sentence
future multicoredesigns
- p. 3 Section 2/3
FinTETs
- p. 3 Section 2
Sandybrige
- p. 5 Table 3
NComposd
Judge's note: Both are in the page images: p.8, first line of Sec. 7, and p.5, Table 3 'Composed' block. The FinTETs and Sandybrige items in this cluster are already covered by C017.
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Typo Table 3 subscript misspelled: "NComposd(qL, qS)", while the speedup formula directly below uses "NComposed".
- p. 5 Table 3, Composed row
NComposd(qL, qS )
- p. 5 Table 3, Composed row
NComposd
Judge's note: Visible in the crop of Table 3 on p5.
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Typo 'per-core power of 15.63 W and are of 22.30 mm2' should read 'area of'.
- p. 8 Section 7.1, T9900 example
and are of 22.30 mm2
- p. 8 Section 7.1
per-core power of 15.63 W and are of 22.30 mm2
Judge's note: The p.8 image (Sec. 7.1, right column) shows 'are of 22.30 mm²'.
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Typo Reference [14] title misspells 'power-constrained' as "power-contrained" ("Navigo: An early-stage model to study power-contrained architectures and specialization").
- p. 12 Reference [14]
power-contrained architectures
Judge's note: Seen in the crop of page 12, reference [14]: the text reads "power-contrained architectures". This is a misspelling of 'constrained'. It is cosmetic.
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Typo References [20] and [21] end with a stray ", ." after the venue: "In ICDCN ’09, ." and "In ISCA ’10, ."
- p. 12 Reference [20]
In ICDCN ’09, .
- p. 12 Reference [21]
ISCA ’10, .
Judge's note: Seen in the crops of page 12: both references end with a comma followed by a lone period after the italic venue name. The other references end with just a period after the venue. This looks like an empty bibliography field left over in formatting. It is cosmetic.
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