Amdahl's Law in the Multicore Era
Computer, 2008 · paper · Computer science
Extends Amdahl's law with a simple hardware cost model for multicore chips, where core resources are measured in base core equivalents. It considers symmetric and other designs and urges designers to consider whole-chip performance, noting limitations of the models.
Checked: PDF from research.cs.wisc.edu, fetched 4 Oct 2026. Page numbers are those of that PDF.
3 findings
Substance P.4: "the maximum speedup of 51.2 occurs with 36 cores of 7.1 BCEs each" (repeated in Result 2: "maximum speedup occurs using 7.1 BCEs per core"). Under the stated model the optimum for f=0.975, n=256 is r ≈ 6.56 BCEs (about 39 cores).
- p. 4 Symmetric section, discussion of Figure 2b
the maximum speedup of 51.2 occurs with 36 cores of 7.1 BCEs each
- p. 4 Result 2
maximum speedup occurs using 7.1 BCEs per core
- p. 4 Result 2
the maximum speedup occurs using 7.1 BCEs per core
Only the authors can say what is right here.
Judge's note: The model is Speedup_sym = 1/((1-f)/sqrt(r) + f*sqrt(r)/n) with perf(r) = sqrt(r), and the paper says it uses a continuous approximation (text line ~98). Setting the derivative to zero gives r* = n(1-f)/f = 6.564, so 256/6.564 ≈ 39 cores, with speedup 51.24. At r = 7.1 the speedup is 51.20, which is lower. The printed speedup 51.2 is right after rounding, but the location of the optimum (7.1 BCEs, 36 cores) does not match the stated model. Integer core counts would also favour 39 cores over 36. The authors could say whether a discrete search grid was used.
Second check: another model agreed
Report a problem with this finding
Reference or label Figure 2 panels (c) and (d), titled 'Asymmetric, n = 16' and 'Asymmetric, n = 256', have y-axis label "Speedup_symmetric" where Speedup_asymmetric is expected.
- p. 3 Figure 2, panels (c) and (d), y-axis labels
Speedupsymmetric
Judge's note: The p.3 image shows the y-axes of panels c and d reading Speedup with the subscript 'symmetric'. The caption says '(c, d) asymmetric', and panels e and f use the model-specific label Speedup_dynamic. The axis label is wrong for the plotted quantity.
Second check: another model agreed
Report a problem with this finding
Reference or label Figure 2, all panels: the logarithmically spaced r-BCEs axis has its first tick labelled "0" (0, 2, 4, 8, 16 ...), but the leftmost plotted point is r = 1.
- p. 3 Figure 2, all panels, x-axis 'r BCEs'
0 2 4 8 16
- p. 4 Text describing Figure 2a
a value 1 says the chip has 16 base cores
- p. 3 Figure 2, all panels, x-axis
0
Judge's note: On the p.3 image the ticks 0, 2, 4, 8, 16 are equally spaced in panel a, so the axis is log2 and its leftmost position is r = 1. A log axis cannot contain 0. The curve values at that point match r = 1: f = 0.999 starts near 15.8 and f = 0.5 near 1.9. The p.4 text also says 'a value 1 says the chip has 16 base cores'. The first tick should read 1.
Second check: another model agreed
Report a problem with this finding
5 minor (typos and the like; most checked by the judge only)
Wording Result 6: "comparable asymmetric speedup of 165". The stated model's maximum for f=0.99, n=256 is about 165.7 (r ≈ 41–42), while 222.6 in the same sentence is rounded up to 223.
- p. 5 Result 6
comparable asymmetric speedup of 165
Judge's note: I recomputed Speedup_asym = 1/((1-f)/sqrt(r) + f/(sqrt(r)+n-r)). The maximum is about 165.75 at r = 41–42, and r = 36 gives 165.4. The dynamic value 1/(0.01/16 + 0.99/256) = 222.6 is printed as 223. So one value appears truncated and the other rounded. The difference is small, and either convention could be intended.
Second check: another model agreed
Report a problem with this finding
Typo P.5: "question the validity of Amdhal’s law to future systems". 'Amdhal' should be 'Amdahl'.
- p. 5 Simple as Possible, but No Simpler, third paragraph
validity of Amdhal’s law to future systems
- p. 5 Simple as Possible, para 3
validity of Amdhal’s law
- p. 5
question the validity of Amdhal’s law to future systems
Judge's note: The p.5 image shows 'Amdhal’s'. The name is spelled 'Amdahl' everywhere else in the paper.
Second check: none (judge only)
Report a problem with this finding
Typo Acknowledgments: "CCR-0324878, CNS-0551401, CNS-0720565, and CNS-0720565". The same grant number is listed twice.
- p. 5 Acknowledgments
CNS-0720565, and CNS-0720565
- p. 5
CCR-0324878, CNS-0551401, CNS-0720565, and CNS-0720565
Only the authors can say what is right here.
Judge's note: The p.5 image confirms that the grant list gives CNS-0720565 twice. Only the authors can say which grant number was meant for the second entry.
Second check: none (judge only)
Report a problem with this finding
Typo Reference 6: "J.A. Kahl et al., “Introduction to the Cell Multiprocessor,”". The first author's surname is likely Kahle.
- p. 6 Reference 6
J.A. Kahl et al., “Introduction to the Cell Multiprocessor,”
Only the authors can say what is right here.
Judge's note: Rests on outside knowledge: that the first author of the IBM J. R&D 2005 Cell paper is J.A. Kahle. The p.6 image confirms the printed name is 'Kahl'.
Second check: none (judge only)
Report a problem with this finding
Typo Reference 13: "Scalability of Asymetric Cluster Chip Multiprocessors". 'Asymetric' should be 'Asymmetric'.
- p. 6 Reference 13
Scalability of Asymetric Cluster Chip Multiprocessors
Judge's note: The p.6 image confirms 'Asymetric' in the reference 13 title. The paper spells 'asymmetric' correctly everywhere else.
Second check: none (judge only)